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Enhanced Serial Audio Interface Timing
62
63
SCKR
(Input/Output)
FSR (Bit)
Out
65
64
66
FSR (Word)
Out
69
71
72
70
Data In
FSR (Bit)
In
FSR (Word)
In
Flags In
73
75
74
76
First Bit
Last Bit
75
77
Note:
Figure 15 is drawn assuming positive polarity bit clock (RCKP=0) and positive
frame sync polarity (RFSP=0).
Figure 15. ESAI Receiver Timing
HCKT
SCKT (output)
96
97
Note: Figure 16 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity
(TCKP=0).
Figure 16. ESAI HCKT Timing
DSP56371 Data Sheet, Rev. 4.1
52
Freescale Semiconductor
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